1. Field of the Invention
The invention relates to IGFET (insulated gate field effect transistor) circuits and particularly to resistive devices and circuits for holding a capacitive node substantially at a voltage supply level.
2. Brief Description of the Prior Art
Typical logic circuits, such as logic gates or inverters and other circuits implemented using IGFETs have switch devices, which are IGFETs connected to a "ground" voltage supply and having their gate electrodes connected to inputs of the logic gate or inverter thereby implemented. Such logic circuits also usually include a load IGFET having its drain connected to a voltage supply conductor or clock conductor and its source connected to the drain of the one or more switch IGFETS. The gate of the load IGFET may be connected to its drain, or it may be connected to a clock conductor. The clock signal may be generated externally, or may be generated on an integrated circuit chip with the subject logic circuit. For dynamic IGFET circuits, the output node is charged up to a logical "1" level, but after the clock pulse or signal causing such charging disappears, the voltage level of the output is sustained by virtue of charge stored on capacitance associated with the output node. Usually there are parasitic leakage current paths which will cause a gradual discharge of the output voltage if the clock pulse does not reappear and charge the voltage to a full logical 1 level. Diffused resistors connected between the output node and a supply voltage conductor have been utilized as level sustaining devices. Also, in silicon gate IGFET circuits, polycrystalline silicon resistors have been utilized. However, such resistors normally need to be of very high resistance in order to reduce power consumption. Consequently, the amount of chip area required by such resistors is very large. Further, such resistors cause additional capacitive loading on the output node, which undesireably reduces switching speed.